IEEE STUDENT CHAPTER conducting two days workshop on
“FPGA BASED VLSI DESIGN USING VERILOG WITH PRACTICAL IMPLEMENTATION”on 19th to 20th December-2013, in association with ELEGANT TECH.
for more details contact
ECE, HOD

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VJIT is just a average clg. Its neither bad nor good thats how i felt when i studied, factuality is good, supportive bit management isn't.
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